How to write test benches in vhdl

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Testbenches — FPGA designs with VHDL documentation In part 2, we described the VHDL logic of the CPLD for this design. Note that, testbenches are written in separate VHDL files as shown in Listing 10.2. Simplest way to write a testbench, is to invoke the ‘design for testing’ in the testbench and provide all the input values in the file, as explained below, Explanation Listing 10.2

VHDL Test Benches In part 3, we will show the entire VHDL design and the associated tests used to prove that we have, in fact, designed what we started out to design. Purpose of test benches • Structure of simple test bench – Side note about delay modeling in VHDL • Better test benches – Separate, better reusable stimulus generation – Separate sink from the response – File handling for stimulus and response • Example and conclusions • Lots of miscellaneous self-study material

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